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DLX (21)

See Also:
Sites:

http://www.ics.forth.gr/carv/aspida/
» ASPIDA Project Open in a new browser window
   ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.
   http://www.ics.forth.gr/carv/aspida/
http://arstechnica.com/etc/books/comp-arc.html
» Computer Architecture: A Quantitative Approach Open in a new browser window
   Book review, explains that book is a classic and standard work in its field. Ars Technica.
   http://arstechnica.com/etc/books/comp-arc.html
http://www.cs.cinvestav.mx/SC/prof_personal/adiaz/vhdl/DLX/index.htm
» DLX Architecture Open in a new browser window
   Introductory HTML slide show.
   http://www.cs.cinvestav.mx/SC/prof_personal/adiaz/vhdl/DLX/index.htm
http://www.erc.msstate.edu/mpl/distributions/scmos/html/dlx.html
» DLX CPU in SCMOS Open in a new browser window
   Photo with descriptions.
   http://www.erc.msstate.edu/mpl/distributions/scmos/html/dlx.html
http://www.hpc.msstate.edu/mpl/education/docs/dlx/
» DLX Implementation at MSU Open in a new browser window
   Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), MSU Engineering Research Center; used as design driver to help validate standard cell libraries.
   http://www.hpc.msstate.edu/mpl/education/docs/dlx/
http://www.ece.umd.edu/class/enee350h.F2005/dlx.html
» DLX Information Open in a new browser window
   Documents: getting started, instruction set summary and description, simulator manual.
   http://www.ece.umd.edu/class/enee350h.F2005/dlx.html
http://www.eng.tau.ac.il/~guy/Computer_Structure03/slides/instructions.pdf
» DLX Instruction Slides Open in a new browser window
   Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University.
   http://www.eng.tau.ac.il/~guy/Computer_Structure03/slides/instructions.pdf
http://www.cse.lehigh.edu/~caar/lou/dlx.html
» DLX in VHDL Open in a new browser window
   VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.
   http://www.cse.lehigh.edu/~caar/lou/dlx.html
http://cobweb.ecn.purdue.edu/~teamaaa/dlxview/
» DLXview Open in a new browser window
   Interactive visual pipeline simulator using DLX instruction set; operation of pipelined processor is easier to understand than trying to imagine operation from text descriptions; modified and extended from DLXsim. Documents, downloads.
   http://cobweb.ecn.purdue.edu/~teamaaa/dlxview/
http://www.ece.neu.edu/faculty/kaeli.html
» David R. Kaeli, Professor Open in a new browser window
   Director of Northeastern University Computer Architecture Research Laboratory, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links.
   http://www.ece.neu.edu/faculty/kaeli.html
http://www.cs.umd.edu/class/fall2001/cmsc411/proj01/DLX/
» Implementation of 5-stage DLX Pipeline Open in a new browser window
   Introductory tutorial with definitions, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience.
   http://www.cs.umd.edu/class/fall2001/cmsc411/proj01/DLX/
http://www.soe.ucsc.edu/~sbrandt/courses/Spring02/111/dlxos.html
» Introduction to Operating Systems Open in a new browser window
   DLXOS information needed for programming, from introductory course on OSs.
   http://www.soe.ucsc.edu/~sbrandt/courses/Spring02/111/dlxos.html
http://heather.cs.ucdavis.edu/~matloff/dlx.html
» Norman Matloff's DLX Tutorial Open in a new browser window
   Information on DLX processor simulator and compiler, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution.
   http://heather.cs.ucdavis.edu/~matloff/dlx.html
http://www.kroening.com/diplom/
» Out of Order Execution Open in a new browser window
   Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Uses DLX. HTML, PS, GZ, PDF.
   http://www.kroening.com/diplom/
http://www.rs.tu-darmstadt.de/downloads/docu/dlxdocu/SuperscalarDLX.html
» Superscalar DLX Processor Open in a new browser window
   Diagram, description, download.
   http://www.rs.tu-darmstadt.de/downloads/docu/dlxdocu/SuperscalarDLX.html
http://portal.acm.org/citation.cfm?id=546884
» The DLX Instruction Set Architecture Handbook Open in a new browser window
   By Philip M. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal.
   http://portal.acm.org/citation.cfm?id=546884
http://www.csee.umbc.edu/courses/undergraduate/411/spring96/dlx.html
» The DLX Processor Open in a new browser window
   Class overview with tables (instruction format, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland.
   http://www.csee.umbc.edu/courses/undergraduate/411/spring96/dlx.html
http://eceweb.uccs.edu/wang/ECE4480/DLXverilog.pdf
» Verilog Model for DLX Processor Open in a new browser window
   PDF slides, mostly code.
   http://eceweb.uccs.edu/wang/ECE4480/DLXverilog.pdf
http://en.wikipedia.org/wiki/DLX
» Wikipedia: DLX Open in a new browser window
   Encyclopedia article with links to many related topics.
   http://en.wikipedia.org/wiki/DLX
http://cs.uns.edu.ar/~jechaiz/arquitectura/windlx/windlx.html
» WinDLX Open in a new browser window
   Program for MS Windows, an assembly interpreter for DLX assembly language; instructions, source code, downloads. By Javier Echaiz, National University of the South.
   http://cs.uns.edu.ar/~jechaiz/arquitectura/windlx/windlx.html

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